View CXD1261AR_4265326.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the CXD1261AR is an ic which generates the sync signals and timing signals required for a camera system that uses the monochrome ccd image sensor (760h) such as the icx038/039 and icx058/059. features compatible with monochrome (eia/ccir) systems built-in electronic shutter function built-in driver for the horizontal (h) clock built-in sg and tg functions applications ccd camera systems structure silicon gate cmos absolute maximum ratings (ta = 25?, vss = 0v) supply voltage v dd v ss ?0.5 to +7.0 v input voltage v i vss ?0.5 to v dd + 0.5 v output voltage v o vss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 5.0 0.25 v operating temperature topr ?0 to +75 ? ?1 CXD1261AR e95735c12-ps sync signal, timing signal generator for ccd cameras sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin lqfp (piastic)
?2 CXD1261AR pin configuration 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 v ss xv4 xsg2 xv3 xsg1 xv1 xv2 xsub v dd rg v ss tst3 h2 tst2 h1 v dd vr/fld htsg v dd ext v ss tst10 tst11 v dd tst12 tst13 v ss tst14 tst15 tst16 cblk sync hd vd cl d1 d2 tst1 trig v ss osci osco ckin enb ed0 ed1 ed2 ps hr v dd tst9 pblk clp4 clp3 clp2 clp1 v ss tst8 tst7 tst6 tst5 tst4 shd shp mode name pin no. preset l h d1 d2 enb ed0 ed1 ed2 ps ext tst1 tst13 4 5 12 13 14 15 16 52 6 58 l l h h h h h l eia ccir field readout frame readout normal shutter shutter speed serial input parallel input internal external normally high normally low note) normally open for tst except as shown in the above table. ? during frame accumulation (readout), low-speed shutter does not operate normally. ? ?
3 CXD1261AR pin no. symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 i/o description hd vd cl d1 d2 tst1 trig v ss osci osco ckin enb ed0 ed1 ed2 ps v dd h1 tst2 h2 tst3 v ss rg v dd xsub xv2 xv1 xsg1 xv3 xsg2 xv4 v ss o o o i i i i i o i i i i i i o i o i o o o o o o o o horizontal drive pulse vertical drive pulse ckin 2 frequency divided output (eia: 14.318mhz, ccir: 14.1875mhz) mode switching; low: eia; high: ccir (with pull-down resistor) mode switching; low: field readout; high: frame readout ? (with pull-down resistor) test input, fixed to high shutter speed setting pulse (with pull-up resistor) gnd oscillating cell input oscillating cell output clock input (eia: 28.636mhz, ccir: 28.375mhz) shutter switching; low: normal; high: shutter (with pull-up resistor) shutter speed control (with pull-up resistor) shutter speed control (with pull-up resistor) shutter speed control (with pull-up resistor) shutter speed setting method switching; low: serial; high: parallel (with pull-up resistor) power supply horizontal register drive clock test input, normally open (with pull-down resistor) horizontal register drive clock test input, normally open (with pull-down resistor) gnd reset gate pulse power supply discharge pulse vertical register drive clock vertical register drive clock sensor charge readout pulse vertical register drive clock sensor charge readout pulse vertical register drive clock gnd pin description ? the ccd image sensor characteristics are guaranteed for field accumulation operation.
4 CXD1261AR 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 shp shd tst4 tst5 tst6 tst7 tst8 v ss clp1 clp2 clp3 clp4 pblk tst9 v dd hr vr/fld htsg v dd ext v ss tst10 tst11 v dd tst12 tst13 v ss tst14 tst15 tst16 cblk sync o o o o o o o o o o o o o i i i i i o o i o o o o o precharge level sample-and-hold pulse data sample-and-hold pulse test output, normally open test output, normally open test output, normally open test output, normally open test output, normally open gnd clamp pulse clamp pulse clamp pulse clamp pulse blanking cleaning pulse test output, normally open power supply h reset pulse v reset pulse (fld output when ext = low) htsg input; low: xsg1, 2 on; high: off (valid only when ext = low) fixed to low when ext = high power supply sync mode switching; low: internal; high: external sync (with pull-down resistor) gnd test input, normally open (with pull-down resistor) test output, normally open power supply test output, normally open test input, fixed to low gnd test output, normally open test output, normally open test output, normally open composite blanking pulse composite sync pulse pin no. symbol i/o description
5 CXD1261AR block diagram 18 20 23 25 26 27 28 29 30 31 33 41 42 43 45 63 48 49 50 52 7 12 13 14 15 16 9 10 11 3 4 5 2 64 1 cl h counter 1/910 or 1/908 v counter 1/525 or 1/625 decoder decoder pulse generator reset generator htsg fld xsub shutter control 1/2 high-speed pulse generator mode setting cl rg h1 h2 shp xv3 xv4 xsg1 xsg2 xsub xv1 xv2 clp3 clp1 clp2 pblk hd vd cblk sync vr/fld htsg ext hr ed0 ed1 enb ps ed2 trig osci osco ckin cl d1 d2 34 shd
6 CXD1261AR electrical characteristics 1) dc characteristics (v dd = 5v 0.25v, topr = 20 to +75 c) 2) i/o pin capacitance (v dd = v 1 = 0v, f m = 1mhz) item symbol conditions min. typ. max. unit supply voltage input voltage output voltage 1 ? 1 output voltage 2 ? 2 output voltage 3 ? 3 output voltage 4 ? 4 feedback resistor pull-up resistor pull-down resistor v dd v ih1 v il1 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 r fb r pu r pd i oh = 2ma i ol = 4ma i oh = 4ma i ol = 8ma i oh = 8ma i ol = 8ma i oh = 2ma i ol = 2ma v in = v ss or v dd v il = 0v v ih = v dd 4.75 0.7v dd v dd 0.5 v dd 0.5 v dd 0.5 v dd /2 500k 40k 40k 5.0 2m 100k 100k 5.25 0.3v dd 0.4 0.4 0.4 v dd /2 5m 250k 250k v v v v v v v v v v v ? ? ? item symbol min. typ. max. unit input pin capacitance output pin capacitance input/output pin capacitance c in c out c i/o 9 11 11 pf pf pf note) ? 1 clp1, clp2, clp3, clp4, pblk, cblk, sync, vr, hd, vd, xsub, xsg1, xsg2, xv1, xv2, xv3, xv4 ? 2 cl, rg, shp, shd ? 3 h1, h2 ? 4 osco
7 CXD1261AR external reset description h reset (hr) the reset is performed at the first falling edge of the reset pulse that was input; resets are not performed at subsequent edges as long as they do not deviate by two clock pulses (0.14s) or more. the minimum reset pulse width is 0.35s. in addition, hd immediately after a reset can not be guaranteed. the position at which the reset is performed is 2.31s advanced after the h reset input. h reset input hd output 0.35s or more 2.31s v reset (vr) the falling edge of v reset pulse that was input is field identified by the phase difference with the internal signal (field judge pulse) defined by the falling edge of hd. and vd is reset in phase with v reset pulse. when field judge pulse is low and v reset pulse falls, eia: vd falling edge after 262.5h is the relation between hd and vd of even field. ccir: vd falling edge after 313.5h is the relation between hd and vd of odd field. also, when field judge pulse is high and v reset pulse falls, eia: vd falling edge after 262.5h is the relation between hd and vd of odd field. ccir: vd falling edge after 313.5h is the relation between hd and vd of even field. the minimum reset pulse width is 64s. hd output field judge pulse vr input vd output (eia) vd output (ccir) 1hd 12 3 262 (312) 263 (313) 264 (314) the value without ( ) is for eia the value in ( ) is for ccir 1hd note: for ccir, vd output is delayed 1hd in relation to vr input. vd timing is genarated after 262.5h with this vr timing vd timing is genarated after 313.5h with this vr timing 64s or more
8 CXD1261AR electronic shutter description (during frame accumulation, low-speed shutter does not operate normally.) the xsub pulse timing changes according to the electronic shutter control described below. in addition, the enb pin controls whether the xsub pulse is output or not; this control has priority. 1. continuously variable shutter (trigger mode) when using the normal shutter, either leave the trig pin open or connect it to the power supply. when using the continuous variable shutter, input the clock pulse to the trig pin. the shutter speed is determined by sampling the xsub pulse during the interval between the falling edge of xsg1 and the falling edge of trig, and then stopping the xsub pulse during the interval between the falling edge of trig and the next falling edge of xsg1. when using the trig pin to control the shutter speed, in order to broaden the control range it is necessary to use the ed0, 1, and 2 pins (described later) to set the shutter speed to 1/10000. 2. normal shutter 2-1. switching between parallel input and serial input parallel input or serial input can be selected as the method for inputting the data used to determine the shutter speed. parallel input (ps = high): permits selection of eight shutter speeds by using three bits ed0, ed1, and ed2. serial input (ps = low): shutter speed is determined by inputting the strobe to ed0, clk to ed1, and the data to ed2. shutter speed vd hd xsg1 trig xsub
9 CXD1261AR d1 x l h l h x x x x x x enb l h h h h h h h h h h ed0 x h h l l h l h l h l ed1 x h h h h l l h h l l ed2 x h h h h h h l l l l shutter speed shutter off 1/60 (s) 1/50 (s) 1/100 (s) 1/120 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/4000 (s) 1/10000 (s) flickerless l l high-speed shutter l h mode smd1 smd2 low-speed shutter h l no shutter h h 2-2. when using parallel input (ps = high) shutter speed table only the high-speed shutter is used when using parallel input (during frame accumulation, low-speed shutter does not operate normally.) 2-3. when using serial input (ps = low) the following four modes can be selected according to the combination of serial data smd1 and smd2. (during frame accumulation, low-speed shutter does not operate normally.) shutter mode flickerless: eliminates flicker resulting from the frequency of fluorescent light high-speed shutter: higher speed shutter than 1/60 (eia), 1/50 (ccir) low-speed shutter: lower speed shutter than 1/60 (eia), 1/50 (ccir) (does not operate normally during frame accumulation.) no shutter: no shutter operation the data on ed2 is latched in the register at the rising edge of ed1 and is then taken in internally while ed0 is low. d0 d1 d2 d3 d4 d5 d6 d7 d8 smd1 smd2 dummy ed1 (clk) ed2 (data) ed0 (stb) ? 1 ? 2 ? 2 ? 1 xsub (shutter pulse) is not generated. ? 2 accumulation time is as follows regardless of field accumulation/frame accumulation. d1 = low (eia), 1/60 (s) d2 = high (ccir), 1/50 (s) (pseudo field readout during frame accumulation.)
10 CXD1261AR ed2 setup time against the rising edge of ed1 ed2 hold time against the rising edge of ed1 ed1 rising setup time against the rising edge of ed0 ed0 pulse width ed0 rising setup time against the rising edge of ed1 symbol t s2 t h2 t s1 t wo t so min. 20ns 20ns 20ns 20ns 20ns max. 50s load value 0fa 16 0fc 16 100 16 108 16 118 16 137 16 176 16 196 16 calculated value 1/10169 1/4435 1/2085 1/1012 1/499 1/252 1/125 1/100 shutter speed 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/100 load value 0c8 16 0ca 16 0ce 16 0d6 16 0e6 16 105 16 143 16 149 16 calculated value 1/10040 1/4394 1/2068 1/1004 1/495 1/250 1/125 1/120 shutter speed 1/1000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/100 eia ccir shutter speed (fld) 2 4 : 508 510 load value 1fe 16 1fd 16 : 101 16 100 16 ed2 ed1 ed0 t s2 t h2 t s1 t s0 t w0 (during frame accumulation, low-speed shutter does not operate normally.) high-speed shutter for eia t = [262 10 (1ff 16 l 16 ) ] 63.56 + 34.78s ? l 16 : load value for ccir t = [312 10 (1ff 16 l 16 ) ] 64 + 35.6s low-speed shutter (does not operate normally during frame accumulation.) n = 2 (1ff 16 l 16 ) fld however, 1ff cannot be used as the load value.
11 CXD1261AR hd vd sync cblk fld odd field even field hd vd sync cblk fld odd field even field timing chart (eia)
12 CXD1261AR hd vd sync cblk fld hd vd sync cblk fld odd field even field odd field even field timing chart (ccir)
13 CXD1261AR 0 91 910 21 476 861 511 406 154 56 hd hsync eq vsync cblk vd fld s y n c 1/2h 1h timing chart (eia) 0 91 908 21 475 859 510 405 167 56 hd hsync eq vsync cblk vd fld s y n c 1/2h 1h timing chart (ccir) unit: clock pulses unit: clock pulses
14 CXD1261AR fld cblk/vd hd xsg1 xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 field frame xsg2 timing chart (eia vertical direction) odd field
15 CXD1261AR fld cblk/vd hd xsg2 xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 field frame xsg1 timing chart (eia vertical direction) even field
16 CXD1261AR fld cblk/vd hd xsg1 xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 field frame xsg2 timing chart (ccir vertical direction) odd field
17 CXD1261AR fld cblk/vd hd xsg2 xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 field frame xsg1 timing chart (ccir vertical direction) even field
18 CXD1261AR hd ck cl h1 h2 rg shp shd xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk the black-pointed sections of the h1 clock indicate the optical black. timing chart (eia horizontal direction)
19 CXD1261AR hd ck cl h1 h2 rg shp shd xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk the black-pointed sections of the h1 clock indicate the optical black. timing chart (ccir horizontal direction)
20 CXD1261AR 578 3 36 36 36 36 22 36 33 3 36 3 hd xv4 odd xv1 xv2 xv3 xv4 even xv1 xv2 xv3 xv4 odd xv1 xv2 xv3 xv4 even xv1 xv2 xv3 xsg2 xsg1 field readout frame readout unit: clock pulses (1ck = 69.84ns) readout timing chart (eia)
21 CXD1261AR 589 3 36 36 36 36 22 36 33 3 36 3 hd xv4 odd xv1 xv2 xv3 xv4 even xv1 xv2 xv3 xv4 odd xv1 xv2 xv3 xv4 even xv1 xv2 xv3 xsg2 xsg1 field readout frame readout unit: clock pulses (1ck = 70.48ns) readout timing chart (ccir)
22 CXD1261AR timing chart (high-speed phase) ckin cl h1 h2 rg shp shd application circuit 48 33 116 49 64 32 17 CXD1261AR shutter control ccd image sensor signal processing osc eia : 28.6363mhz ccir : 28.375mhz ? use a crystal that operates with a fundamental wave. v driver application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
23 CXD1261AR package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin 42/copper alloy package structure 12.0 0.2 ? 10.0 0.1 (0.22) b 1 16 17 32 33 48 49 64 0.1 0.1 0.5 0.2 0? to 10? 64pin lqfp (plastic) lqfp-64p-l01 p-lqfp64-10x10-0.5 0.3g detail a 0.5 0.2 (11.0) a 1.5 ?0.1 + 0.2 0.1 solder plating note: dimension ? does not include mold protrusion. 0.13 m 0.5 b = 0.18 ?0.03 ( 0.18 ) (0.127) + 0.08 0.127 ?0.02 + 0.05 detail b : solder
24 CXD1261AR sony corporation package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 12.0 0.2 ? 10.0 0.1 (0.22) b 1 16 17 32 33 48 49 64 0.1 0.1 0.5 0.2 0 ? to 10 ? 64pin lqfp (plastic) lqfp-64p-l01 p-lqfp64-10x10-0.5 0.3g detail a 0.5 0.2 (11.0) a 1.5 0.1 + 0.2 0.1 palladium plating note: dimension ? does not include mold protrusion. 0.13 m 0.5 b = 0.18 0.03 0.125 0.04 detail b : palladium

▲Up To Search▲

Price & Availability of CXD1261AR

	To Download CXD1261AR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .